Superconducting digital systems have inherent advantages as illustrated by the data-center-in-a-shoebox having superlative 3D compute density, interconnect bandwidth, latency, clock rate, and energy efficiency. Demonstration of a high-end, out-of-order CPU is a near-term goal. On the fabrication side, this requires a stackup with 16 superconducting NbTiN wire & via layers, self-shunted a-silicon barrier Josephson Junctions (JJs), and low loss, high-k tunable hafnium–zirconium oxide (HZO) capacitors. Electrical measurements of these three unit process modules are reported: 50 nm interconnects with critical temperature of 13 K and critical current density JC = 120 mΑ/μm2, 210 nm amorphous Si barrier JJs with JC = 0.8 mΑ/μm2 and ICRN = 1.1 mV, and tunable HZO MIM capacitors with specific capacitance of 28 fF/μm2 and k-value of 30. All devices were fabricated on 300 mm wafers with thermal budget of 420 C, compatible with standard CMOS processes. On the design side, this requires Pulse-Conserving Logic (PCL) that reproduces all the functions of a standard CMOS gate library. Wave-pipelined, SFQ-pulse-driven Josephson SRAM (JSRAM) memory operates with the same clock rate and energy efficiency as for the logic. Such circuits implement efficient signal fanout in the array. Design of an associative memory array is reported that constitutes a key, historically difficult building block of the out-of-order CPU.