Random number generators are often needed to execute scientific software simulations, statistical analysis, cryptography and various fields of data processing algorithms. High-speed random number generations are usually implemented by using hardware random number generators (HRNGs) based on some uncertain physical phenomenon to get the source of random numbers. We have proposed an oscillator-based RNG using Josephson oscillation and single flux quantum (SFQ) logic circuits as such one of HRNGs [1]. The proposed HRNG has already been designed, fabricated using Nb/AlOx/Nb junction circuit technology and successfully tested. Though the HRNG generates stochastic binary numbers of “0” or “1” with the ratio of 50:50, the ratio may slightly shift from the ideal ratio due to variations of circuit parameters or the change of power supply voltage. In this report, a HRNG with a complementary structure is proposed to reduce simply such shifting from the ideal ratio of binary numbers. The proposed structure of a HRNG consists of two HRNGs which are an original one and another one with inverted outputs. This combination of two HRNGs is aimed at the generation ratio of random numbers compensated each other. The proposed HRNG is designed using process parameters of the AIST Nb high-speed standard process (HSTP) [2] with 10 kA/cm2 Nb/AlOx/Nb junctions. The improvement of the bias dependence of the random number generation rate is confirmed by numerical simulations of the designed circuits. Furthermore, the HRNG is fabricated using HSTP technology and tested. A random number generation based on a low-speed functional test is successfully confirmed. The measurement results show less bias dependence of the random number generation rate.
[1] T. Onomi and Y. Mizugaki, “Hardware Random Number Generator Using Josephson Oscillation and SFQ Logic Circuits,” IEEE Trans. Appl. Superconduct., vol. 30, no. 7, p. 1301305, Oct. 2020.
[2] Takeuchi, N., S. Nagasawa, F. China, T. Ando, M. Hidaka, Y. Yamanashi, and N. Yoshikawa, “Adiabatic quantum-flux parametron cell library designed using a 10 kA cm-2 niobium fabrication process," Supercond. Sci. Technol., Vol. 30, 035002, 2017.
This research was supported by JSPS KAKENHI Grant Numbers 18K11231 and 23K11042. This research was partly supported by VLSI Design and Education Center (VDEC), the University of Tokyo, in collaboration with Cadence Design Systems, Inc. The circuits were fabricated in the clean room for analog-digital superconductivity (CRAVITY) of the National Institute of Advanced Industrial Science and Technology (AIST) with HSTP. The authors thank Prof. Y. Mizugaki for technical supports of the low-temperature measurements.