Abstract Body

RSFQ circuits have attracted attention for their application to qubit control circuits because of their high-speed operation, low power consumption, and cryogenic operation [1]. Controlling qubits requires a clock generator with a stable long-term oscillation frequency. An all-digital phase locked loop (ADPLL) is one of the circuitry solutions to achieve this. It is a circuit including a digitally controlled oscillator (DCO), which is a variable frequency oscillator, and it synchronizes itself with an external clock by negative feedback control. The SFQ-based ADPLL in the previous study [2] detected earlier one of the reference or the internal signal and then, increased or decreased the frequency of the internal signal by one predefined step for one reference period, where the acceptable initial phase difference was not provided. In this study, a time-to-digital converter (TDC) was introduced into the ADPLL to determine the time difference of the reference and the internal signal, which enabled to make and several improvements on the circuit performance.

A block diagram of the designed ADPLL is shown in Fig.1(a). The TDC is a circuit which generates a 2-bit digital output (-4, -3, -2, -1, +1, +2, +3, or +4) corresponding to the time difference between the external clock (reference) and the internal clock (internal signal). It determines the time difference by using the outputs of the last 3 TFFs in the 1/2^M divider. By eliminating the “0” output from the TDC, its time resolution is enhanced to the detection limit of the SFQ circuit cells. The output of the TDC corresponds to the proportional (P) control. To reduce the simple harmonic motion, a proportional-derivative (PD) controller is added to reduce the simple harmonic motion.

The DCO is a ring oscillator which consists of multiple tunable delay JTLs (TDJTLs) [2] with the same parameters. In order to control the oscillation frequency, it requires signals to switch between slow/fast mode for each cell in the TDJTLs. The DCO controller is the circuit for converting the serial output from the PD controller into a frequency control word (FCW) for the DCO. In order to process the continuous Up'/Down' signals input, the throughput of the DCO controller has been improved by making it indefinite which cell in the TDJTLs will be fast mode.

For the circuit design, we used the RSFQ digital cell library "CONNECT" updated for the Nb/AlOx/Nb 10kA/cm² process (AIST-HSTP) [3]. In addition, we designed a layout of the TDJTL cell with its parameter optimization for expanding operating margins.

Numerical simulation was performed to verify the ADPLL with the target frequency set at 20 GHz. By setting the number of TDJTLs in the DCO to 4 and the bias voltage to 109.6 % of the nominal bias voltage (2.5 mV × 1.096 = 2.74 mV), the oscillation frequency range of the DCO was from 19.8 GHz to 20.2 GHz. This DCO was incorporated into an ADPLL with a 1/2¹² divider and an external clock of 20 GHz / 2¹² = 4.88 MHz was input to TDC. The initial phase difference between the external clock and the internal clock was set to 180°, and the DCO thermal noise at 4.2 K was approximated by a Gaussian distribution. The time variation of the period difference and phase difference between the clocks are shown in Fig.1(b). Phase locking occurred in 18 μs (88 clock cycles), and it was confirmed that phase locking was achieved even with initial phase difference as large as 180°. The time variation of the output period of the DCO is shown in Fig.1(c). Because of the influence of thermal noise and the limitations of the frequency control performance of the ADPLL, fluctuations in the period with a standard deviation of σ = 0.33 ps occurred.

References

[1] R. McDermott, et al., Phys. Rev. Appl. 2 (2014).
[2] H. Cong, et al., IEEE Trans. Appl. Supercond. 32 (2022).
[3] N. Takeuchi, et al., Supercond. Sci. Technol. 30 (2017).

Acknowledgment

This work was partly supported by JSPS KAKENHI Grant Number JP20H02201. It was also supported through the activities of VDEC, The University of Tokyo, in collaboration with Cadence Design Systems.

Keywords: all-digital phase locked loop (ADPLL), time-to-digital converter (TDC), digitally controlled oscillator (DCO), RSFQ