ED7-3

Design and Demonstration of Single Flux Quantum Stochastic Matrix Multiplier

14:15-14:30 Dec.5

*Yuki Yamanashi1,2,3, Hijiri Okumura4, Nobuyuki Yoshikawa1,2,3
Department of Electrical and Computer Engineering, Yokohama National University, 79-5 Tokiwadai, Hodogaya, Yokohama, Kanagawa, 240-8501 & Japan1
Institute of Advanced Sciences, Yokohama National University, 79-5 Tokiwadai, Hodogaya, Yokohama, Kanagawa, 240-8501 & Japan2
Institute for Multidisciplinary Sciences, Yokohama National University, 79-5 Tokiwadai, Hodogaya, Yokohama, Kanagawa, 240-8501 & Japan3
Graduate School of Environment and Information Sciences, Yokohama National University, 79-7 Tokiwadai, Hodogaya, Yokohama, Kanagawa, 240-8501 & Japan4
Abstract Body

Stochastic computation represents a number by the probability of a “1” occurring in a binary digit number train. This approach enables multiplication and addition to be performed with a minimal number of logic gates and has garnered attention in applications where approximate computation is effective. For stochastic computations, which require calculation of long number trains, the use of superconducting single-flux quantum (SFQ) circuits—capable of high-speed operation—presents a promising solution. Another advantage of the use of the SFQ circuits is the availability of an ultra-fast superconductor random number generator (SRNG) [1].

In this study, we designed and evaluated an SFQ stochastic multiplier, a crucial circuit component in the field of wireless signal processing. Wireless signal processing is well-suited for stochastic computing because it involves numerical values that include quantization errors from analog-to-digital conversion. The matrix multiplier can be implemented using adders and multipliers. We developed an SFQ multiplier intended for operation at 50 GHz. A random number train generated by the SRNG is used as the control signal for the multiplexer. We designed a 2x2 matrix multiplier composed of eight AND gates functioning as adders and four multipliers, all based on SFQ stochastic circuits using the AISE 10 kA/cm^2 Nb high-speed process [2]. The test circuit of the 2x2 matrix multiplier contains approximately 1500 Josephson junctions.

The test circuit was measured at low speed at 4.2 K, the temperature of liquid helium. SRNGs were used to generate the input stochastic number sequences. We experimentally verified the correct operation of one output. The relationship between the output and the input as well as the multiplexer control signals was measured. The output exhibited errors consistent with numerical analysis.

We believe this is the first demonstration of a stochastic arithmetic circuit operating with SFQ circuits. The designed matrix multiplication circuit is expected to be valuable in not only wireless signal processing but also various applications, including image processing and neural networks.

References

[1] Y. Yamanashi and N. Yoshikawa, “Superconductive Random Number Generator Using Thermal Noises in SFQ Circuits,” IEEE Trans. Appl. Supercond., vol. 19, no. 3, pp. 630–633, Jun. 2009.

[2] M. Hidaka and S. Nagasawa, “Fabrication process for superconducting digital circuits,” IEICE Trans. Electron., vol. E104–C, pp. 405–410, Sep. 2021.

Acknowledgment

This work was supported by KAKENHI 22H01542 and 24H00311. The authors thank Naoki Ishikawa for fruitful discussion. The circuits were fabricated in the clean room for analog-digital superconductivity (CRAVITY) of National Institute of Advanced Industrial Science and Technology (AIST) with the high-speed standard process (HSTP).

pict

Figure 1. Micrograph of the SFQ stochastic 2x2 multiplier.

Keywords: SFQ circuit, stochastic computing