Superconducting Single-Flux-Quantum (SFQ) logic circuits have been studied for years. The high-speed ultra low-power logic operation is attractive, while the circuit design requires distinctive ideas to make full use of the nature of the device. We have been designed several SFQ logic circuits and developed design methods for them. In this presentation, we summarize logical aspects of SFQ circuit design and key ideas in the design methods that are different from conventional CMOS design methods.
SFQ logic circuits work based on pulse logic, which is inherently different from two-level logic employed in CMOS circuits. All SFQ logic gates are usually clocked, i.e., the operation is triggered by clock pulses, and the circuits can be designed in similar way as two-level logic. However, the amount of clock wire is not negligible, and the timing constraints at each logic gate require precise physical design. The wiring has become possible with the progress of multi-layer and thin wire routing. The placement and routing methods are expected to make progress. To eliminate the clock wiring, alternative design with asynchronous logic is possible for specific applications. Recently, design with clockless gates, which synchronize by the data pulses' own timing, becomes attractive.
As a natural result of using pulse logic, an output of a gate cannot drive a bus, or multiple gates. A fanout can be implemented as an active splitter, but it increases circuit area and delay. Therefore, logic optimization objective should be adjusted according to the cost, and suitable circuit algorithms should be selected. Development of large-scale memory elements for use under this condition is also expected.
Let us visit the issue of clock distribution and operation timing. As the switching of SFQ gates is very fast, wiring delay is relatively large. In this situation, synchronous design, in which all clocked gates operate at the same time, is not always a best solution.
General synchronous circuit design, in which each clocked gate operates once at a certain point in a clock period but not necessarily simultaneous, can be an effective solution, especially with respect to the clock frequency. Flow-clocking schemes which have long been used in SFQ design fall into this category. In concurrent-flow clocking scheme, the timing to trigger a gate and the successor is skewed. In other words, clocked gates in a circuit are grouped to form pipeline stages, and the timing to trigger the stages are different each other. Here, precise timing design method considering placement and routing constraints is required.
Flow-clocking is advantageous if the computation goes through from the input to the output in one direction, like the cases of stream processing. However, if the results of a stage should be fed back to the previous stages, which is often the case, synchronization is difficult because clock signal among the stages are skewed. Insertion of data buffers could be a solution, but we should be careful not to spoil the merit of high clock frequency. Hierarchical clocking scheme would be also effective. For example, we can design the gate-level flow-clocking micro clock, with the system-level synchronous clock whose cycle is composed of several micro clock cycles.
In logic timing design, we have been focusing on the order of pulse arrival at each gate. Provided that the order is kept, which is a local property, functionality of the circuit is unchanged, which is a global property. Based on this insight, we have been developing schemes for description of circuit specification, formal verification, and static timing analysis.
In summary, SFQ logic family and the derivatives are expected for high-speed low-power computation. To make use of the potential, design ideas and methodologies customized for the device is needed. Though we focused on logic design, issues on device and physical design are also important and cannot be considered separately.