Previously, we have developed a 3-Nb-layer superconducting integrated fabrication process with Nb/Al-AlOx/Al junctions of 6 kA/cm2 critical current density, named SIMIT-Nb03 and a 4-Nb-layer process, named SIMIT-Nb03P. Existing cells in SIMIT-Nb03 wereupdated with the minimal design modification for SIMIT-Nb03P process. We kept developing new circuits with a maximal scale of 1E4 JJs on these two processes, including a SNN circuit (SUSHI) and a 32-bit String-Matching Processor. We then continue our process upgrade by introducing CMP to further increase the critical current density and number of Nb wiring layers, and the resulting 7-Nb-layer 15 kA/cm2 process is named SIMIT-Nb04. Both schematic and layout of cell library have been optimized and re-designed to improve yield and design flexibility compared with those for SIMIT-Nb03. We designed new cells to allow more flexibility in LSI circuit design and new interface cells to allow multi-chip module development. With this new process, we have successfully developed high-frequency SFQ circuits with a scale of 1E3 JJs. Higher working frequency was achieved on this process too, e.g., a PTL ring oscillator worked up to 160 GHz. Meanwhile, we kept developing EDA tools customized for the above processes and cell libraries, supporting key procedures of design automation and verification including RSFQ logic & physical synthesis, superconducting power grid current analysis and timing analysis, which have been fully verified on SIMIT-Nb03, SIMIT-Nb03P, and SIMIT-Nb04. By utilizing the EDA tool chain we developed, an RTL-to-GDSII automation workflow with supply current distribution analysis, static and Monte-Carlo timing analysis can be achieved and the efficiency and reliability of our circuit design are improved.