Adiabatic quantum-flux-parametron (AQFP) is a promising post-CMOS digital logic family in terms of extremely low power consumption and GHz speed operation. Some large-scale integrated circuits, such as a 4-bit microprocessor [1] and a 16-bit bit parallel adder [2], have been designed in AQFP logic and demonstrated at low-speed.
Robust high-speed testing of AQFP circuits is difficult and one of the reasons is the occurrence timing errors caused by clock skews and the delay characteristics of each logic gate. It is necessary to check for timing errors using timing analysis techniques along with logical simulation and verification. Previously, we suggested a validation methodology to characterize the timing parameters including industrial-standard timing check parameters and intrinsic delay parameters of the AQFP logic gate [3].
In this research, we investigated the effect of external thermal noise on the AQFP logic gate. We evaluated the timing characteristics of the AQFP logic gate through bit error rate (BER) analysis so we can further constrain the timing characteristics into an operating region where sufficiently low BER is also achieved. First, we estimate the deep BER characteristics against the clock skew by analog simulation at 5 GHz. The width of the timing window where the BER is below the order of 10-11 is 144 degrees with respect to the clock signal phase difference produced by the clock skew.
In addition, we fabricated a clock skew test circuit on a physical chip with which we can conduct BER analysis. We confirmed that the width of the timing window is 145 degrees and the validity of the simulation estimation result by comparing it with the measurement result at 5 GHz.
[1] C. L. Ayala, et al., “MANA: A monolithic adiabatic integration architecture microprocessor using 1.4 zJ/op unshunted superconductor josephson junction devices,” IEEE J. Solid-State Circuits, vol. 56, no. 4, pp. 1152-1165, Apr 2021
[2] T. Tanaka, et al., “16-bit parallel prefix carry look-ahead kogge-stone adder implemented in adiabatic quantum-fluxparametron logic,” IEICE Trans. Electron., vol. E105.C, no. 6, Jun 2022.
[3] Y. Hoshika, C. L. Ayala, N, Yoshikawa, “In-depth Timing Characterization of Adiabatic Quantum-Flux-Parametron Logic Gate,” IEEE Transaction on Applied Superconductivity, vol. 34, no. 4, pp. 1-8, Jun 2024
This work was supported by JSPS KAKENHI (Grants No. 19H05614 and No. 21K04191). The devices were fabricated in the Superconducting Quantum Circuit Fabrication Facility (Qufab) at the National Institute of Advanced Industrial Science and Technology (AIST).
Keywords: Josephson integrated circuit, Superconducting electronics, AQFP, Gate level modeling