Quantum error correction is a critical technique for transitioning from noisy intermediate-scale quantum devices to fully fledged quantum computers. The surface code, which has a high threshold error rate, is the leading quantum error correction code for two-dimensional grid architecture. So far, the repeated error correction capability of the surface code has not been realized experimentally. Here, we experimentally implement an error-correcting surface code, the distance-three surface code which consists of 17 qubits, on the Zuchongzhi 2.1 superconducting quantum processor. By executing several consecutive error correction cycles, the logical error can be significantly reduced after applying corrections, achieving the repeated error correction of surface code for the first time. This experiment represents a fully functional instance of an error-correcting surface code, providing a key step on the path towards scalable fault-tolerant quantum computing.
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The authors thank the USTC Center for Micro- and Nanoscale Research and Fabrication for supporting the sample fabrication. The authors also thank QuantumCTek Co., Ltd., for supporting the fabrication and the maintenance of room-temperature electronics. This research was supported by the National Key R&D Program of China, Grant No. 2017YFA0304300, the Chinese Academy of Sciences, Anhui Initiative in Quantum Information Technologies, Technology Committee of Shanghai Municipality, National Science Foundation of China (Grants No. 11905217, No. 11774326), Natural Science Foundation of Shanghai (Grant No. 19ZR1462700), and Key-Area Research and Development Program of Guangdong Provice (Grant No. 2020B0303030001).
Figure 1. Layout and circuit implementation. (a) Structure schematic of distance-three surface code. 17 qubits are choosen from Zuchongzhi 2.1 superconducting quantum processor, with 8 data qubits (gray dots), 4Z-type ancilla qubits (green dots), and 4X-type ancilla qubits (red dots). Each pair of qubits is connected with a coupler (black rectangle). Connecting lines are colored according to their involvement in two-qubit gate layers as shown in (b). (b) Circuit for one error correction cycle. Dots on the left are in one-to-one correspondence to those in (a).
Figure 2. Error detection correlation. (a) Correlation matrix for logical |0L> state. The finer scale is used for the marking of ancilla qubits and each block has a definite cycle index. Color scheme is presented in the side color bar with the dark side for low correlation and yellowish side for strong correlation. (b) Correlation matrix for logical |-L> state.
Figure 5. Fidelity of logical state with error detection and/or error correction. (a) Fidelity of the postselected logical |0L> state by error detection as function of clock cycles, i.e., the portion of samples that retain the logical state through some clock cycles. Various lines correspond to different postselection schemes. The dotted line depicts the prediction based on relaxation time T1 of the best physical qubit among all used physical qubits. Logical error rates ϵL are extracted from the curve and logical fidelities TL are calculated. These values are listed by each line. Inset describes the retained rate for the three postprocessing schemes as a function of rounds. (b) Results for the postselected logical |-L> state by error detection. (c) Fidelity of logical |0L> state with the number of surface code cycles with error correction (blue line with square) or without (red line with triangular). (d) Same quantity for the logical |-L> state after error correction
Keywords: Quantum Error Correction, Superconducting Quantum Computing, Surface Code