Abstract Body

Reversible computing [1, 2] can be carried out in a thermodynamically reversible manner, or without energy dissipation. We have been studying reversible circuits using adiabatic quantum-flux-parametron (AQFP) logic [3], which is an energy-efficient superconductor logic family. In this presentation, we report recent research on reversible circuits using AQFP logic. We show the minimum energy dissipation required for general information processing through numerical simulation using reversible circuits comprising a reversible QFP (RQFP) [4], which is a reversible logic gate based on AQFP logic [5]. We also show measurement results of combinational and sequential circuits using RQFP gates for reversible microprocessors [6]. Finally, we show compact reversible circuits using AQFP logic with delay line-based Bennett clocking [7].

References

[1] E. Fredkin and T. Toffoli, Int. J. Theor. Phys., 21, 219–253 (1982).

[2] C. H. Bennett, Int. J. Theor. Phys., 21, 905–940 (1982).

[3] N. Takeuchi et al., Supercond. Sci. Technol., 26, 035010 (2013).

[4] N. Takeuchi et al., Sci. Rep., 4, 6354 (2014).

[5] T. Yamae et al., J. Appl. Phys., 135, 063902 (2024).

[6] T. Yamae et al., Supercond. Sci. Technol., 32, 035005 (2019).

[7] C. H. Bennett, IBM J. Res. Dev., 17, 525–532 (1973).

Acknowledgment

This study was supported by JSPS KAKENHI (Grant No. JP19H05614) and JST, PRESTO (Grant No. JPMJPR22B9), Japan. The circuits were fabricated in the Superconducting Quantum Circuit Fabrication Facility (Qufab) of the National Institute of Advanced Industrial Science and Technology (AIST).

Keywords: Reversible computing, Quantum flux parametron, Adiabatic logic, Bennett clocking

Abstract Body

Our research group developed several types of SFQ digital-to-analog converters (DACs) of SFQ pulse-frequency modulation (PFM), where the SFQ pulse repetition frequency was modulated to generate various values of quantum voltages [1,2]. Since those DACs were intended to be applied to the AC voltage standards, higher resolution was given priority over the synthesized waveform frequencies. One of our DACs fabricated using a 2.5 kA/cm² Nb/AlO_x/Nb integration technology (referred to as the AIST-STP2) synthesized a 47 kHz sinusoidal voltage waveform of 9-bit resolution [1].

In this work, we increased the synthesized waveform frequency up to 1 GHz at the sacrifice of resolution down to 4 bits. In addition, to feed the input digital signal of 16 GHz, we designed an on-chip digital signal generator for a sinusoidal waveform. That is to say, we designed an SFQ-based microwave generator. The configuration is based on a scheme of the direct digital synthesizer (DDS) [3] which is shown in Fig. 1(a). It is composed of a phase register (PR), a phase/amplitude converter (PAC), and a 4-bit DAC. For the 4-bit DAC, we employed our previously-developed DAC of the “sum of selected bit sequence” configuration [4,5].

For circuit designing, we used the RSFQ digital cell library “CONNECT” updated for the 10 kA/cm² Nb/AlO_x/Nb integration process (referred to as the AIST-HSTP) [6]. The CAD layout of the microwave generator excluding a bipolar output voltage multiplier is shown in Fig. 1(b). The total number of Nb/AlO_x/Nb Josephson junctions was 1635. Numerical circuit operation is shown in Fig. 1(c). The number of SFQ pulses for each PR clock period was changed as the sequence of (0, 3, 5, 6, 7, 6, 5, 3, 0, -3, -5, -6, -7, -6, -3, 0), which corresponded to a 1 GHz sinusoidal voltage waveform.

References

[1] Y. Mizugaki, et al., Electronics Lett. 50 (2014) 1637–1639.
[2] Y. Mizugaki, et al., IEICE Electronics Express 13 (2016) 20160242.
[3] V. S. Reinhardt, Proc. IEEE Int. Frequency Cont. Symp., Salt Lake City, 1993, pp. 230–241.
[4] Y. Mizugaki, et al., IEEE Trans. Appl. Supercond. 21 (2011) 3604.
[5] Y. Mizugaki, et al., IEICE Electronics Express 19 (2022) 20220194.
[6] N. Takeuchi, et al., Supercond. Sci. Technol. 30 (2017) 035002.

Acknowledgment

This work was partly supported by JSPS KAKENHI Grant Number JP20H02201. It was also supported through the activities of VDEC, The University of Tokyo, in collaboration with Cadence Design Systems.

Figure 1. (a) Configuration of a microwave generator based on a scheme of the direct digital synthesizer. (b) CAD layout of a designed microwave generator. (c) Numerical results for the circuit operation. The number of SFQ pulses for each PR clock period was changed as the sequence of (0, 3, 5, 6, 7, 6, 5, 3, 0, -3, -5, -6, -7, -6, -3, 0), which corresponded to a 1 GHz sinusoidal voltage waveform.

Keywords: digital-to-analog converter (DAC), RSFQ, direct digital synthesizer (DDS)

Abstract Body

In the realm of superconducting electronics, magnetic Josephson junctions are preferred for memory applications. Most demonstrated devices for this purpose use diffusive ferromagnets, resulting in a reduced I_cR_n product; or a combination of ferromagnet with an insulating layer like AlOx in the form of an SIFS junction, thus achieving reasonable I_cR_n products at the cost of a more complex multi-layer growth process. In this presentation, I will demonstrate a simple tri-layer Josephson memory device using ferromagnetic insulating GdN-based S/FI/S vertical mesa-type junctions, with reliable non-volatile memory operation without the need of a shunt resistor at 4.2 K with characteristic voltages close to 0.2mV[1]. The use of the ferromagnetic insulator layer, results in a straightforward thin film growth and fabrication process which is almost identical to that used for Nb/AlOx/Nb junctions thus probably paving the way for integration of these devices in Rapid Single Flux Quantum circuits.

[1] P. K. Sharma and A. Pal, ‘Shunt-free cryogenic memory using ferromagnetic insulator-based Josephson junctions’, Appl Phys Lett, vol. 125, no. 5, Jul. 2024, doi: 10.1063/5.0211466.

Abstract Body

Adiabatic quantum-flux-parametron (AQFP) is a promising post-CMOS digital logic family in terms of extremely low power consumption and GHz speed operation. Some large-scale integrated circuits, such as a 4-bit microprocessor [1] and a 16-bit bit parallel adder [2], have been designed in AQFP logic and demonstrated at low-speed.

Robust high-speed testing of AQFP circuits is difficult and one of the reasons is the occurrence timing errors caused by clock skews and the delay characteristics of each logic gate. It is necessary to check for timing errors using timing analysis techniques along with logical simulation and verification. Previously, we suggested a validation methodology to characterize the timing parameters including industrial-standard timing check parameters and intrinsic delay parameters of the AQFP logic gate [3].

In this research, we investigated the effect of external thermal noise on the AQFP logic gate. We evaluated the timing characteristics of the AQFP logic gate through bit error rate (BER) analysis so we can further constrain the timing characteristics into an operating region where sufficiently low BER is also achieved. First, we estimate the deep BER characteristics against the clock skew by analog simulation at 5 GHz. The width of the timing window where the BER is below the order of 10-11 is 144 degrees with respect to the clock signal phase difference produced by the clock skew.

In addition, we fabricated a clock skew test circuit on a physical chip with which we can conduct BER analysis. We confirmed that the width of the timing window is 145 degrees and the validity of the simulation estimation result by comparing it with the measurement result at 5 GHz.

References

[1] C. L. Ayala, et al., “MANA: A monolithic adiabatic integration architecture microprocessor using 1.4 zJ/op unshunted superconductor josephson junction devices,” IEEE J. Solid-State Circuits, vol. 56, no. 4, pp. 1152-1165, Apr 2021

[2] T. Tanaka, et al., “16-bit parallel prefix carry look-ahead kogge-stone adder implemented in adiabatic quantum-fluxparametron logic,” IEICE Trans. Electron., vol. E105.C, no. 6, Jun 2022.

[3] Y. Hoshika, C. L. Ayala, N, Yoshikawa, “In-depth Timing Characterization of Adiabatic Quantum-Flux-Parametron Logic Gate,” IEEE Transaction on Applied Superconductivity, vol. 34, no. 4, pp. 1-8, Jun 2024

Acknowledgment

This work was supported by JSPS KAKENHI (Grants No. 19H05614 and No. 21K04191). The devices were fabricated in the Superconducting Quantum Circuit Fabrication Facility (Qufab) at the National Institute of Advanced Industrial Science and Technology (AIST).

Keywords: Josephson integrated circuit, Superconducting electronics, AQFP, Gate level modeling